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Mohamed Zahran

Clinical Associate Professor 
Computer Science Department
Courant Institute of Mathematical Sciences 

Office: WWH 320  
251 Mercer street, Manhattan, NY, 10012

Main    Students    Pulications    Research    Teaching

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Selected Refereed Papers: (for complete list please check my CV )
The following papers are copyrighted, but free for academic usage.

[1] Mahmoud Khairy, Mohamed Zahran, and Amr Wassal, SACAT: Streaming-Aware Conflict-Avoiding Thrashing-Resistant GPGPU Cache Management Scheme, IEEE Transactions on Parallel and Distributed Systems, vol 28, issue 6, June 2017. 

[2] Numair Khan and Mohamed Zahran, Space-efficient Pointwise Computation of the Distance Transform on GPUs, in 7th IEEE Workshop Parallel / Distributed Computing and Optimization 
(PDCO 2017), in conjunction with 31st IEEE International Parallel & Distributed Processing Symposium (IPDPS), May 2017.

[3] Chris Rohlfs and Mohamed Zahran, Optimal Bandwidth Selection for Kernel Regression Using a Fast Grid Search and a GPU, in 7th IEEE Workshop Parallel / Distributed Computing and Optimization (PDCO 2017), in conjunction with 31st IEEE International Parallel & Distributed Processing Symposium (IPDPS), May 2017.

[4] Mohamed Zahran, Heterogeneous Computing: Here to Stay, ACM Queue,  vol 14, No. 6, Nov/Dec 2016, and Communications of the ACM, March 2017.

[5] Mohamed Zahran, Brain-Inspired Machines: What, Exactly, Are We Looking for?, IEEE Pulse, Mar 2016.

[6] Mahmoud Khairy, Mohamed Zahran, and Amr G. Wassal, Efficient utilization of GPGPU cache hierarchy, in the 8th Workshop on General-purpose processing using
GPUs held in conjunction with the 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2015. (pdf)

[7] M. Zahran, Multicore processors: Status quo and future directions, in 10th International Computer Engineering Conference (ICENCO), Dec 2014 (Invited Paper) (pdf).

[8] J. Rajendran, A. K. Kanuparthi, M. Zahran, S. Addepalli, G. Ormazabal, and R. Karri, Securing processors against insider attacks: a circuit-microarchitecture co-design approach,  IEEE Design and Test of Computers, Vol 30, issue 2, Mar/Apr, 2013

[9] Arun K. Kanuparthi, Mohamed Zahran, and Ramesh Karri,  Architecture Support for Dynamic Integrity Checking, IEEE Transactions on  Information Forensics and Security, 
Vol. 7, Issue 1, pp. 321-332, 2012.

[10] H. Chtioui, S. Niar Lamih, R. Ben-Atitallah, M. Zahran, Jl. Dekeyser, andM. Abid,  A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC Architectures,
International Journal of Computer Applications, Volume 47, Number 3, 2012.

[11] Corey Malone,   Mohamed Zahran, and Ramesh Karri,  Are Hardware Performance Counters a Cost Effective Way for Integrity Checking of Programs?, The Sixth ACM Workshop on Scalable Trusted Computing, October 2011. (pdf)

[12] Mohamed Salah Souahi, Smail Niar,  Mohamed Zahran, Mohamed Benmohamed, Towards Dynamic Cache Block Placement for Multi-processor NUCA, IEEE International Conference on Microelectronics, December 2011.

[13] Artem Durytskyy, Mohamed Zahran, and Ramesh Karri,  Improving Robustness of GPUs by Making Use of Faulty Parts, Proc. International Conference on Computer Design  (ICCD11), October 2011. (pdf)

[14] Arun K. Kanuparthi, Mohamed Zahran, and Ramesh Karri, Feasibility Study of Dynamic Trusted Platform Module, Proc. International Conference on Computer Design (ICCD10), 
Amsterdam, October 2010. (pdf)

[15]  Ahmed Youssef, Mohamed Zahran, Mohab Anis, and Mohamed Elmasry,  On the Power Management of Simultaneous Multithreading Processors, IEEE Transactions on VLSI ,  
pp. 1243-1248, Vol. 18, August 2010. (pdf

[16] Mohamed Zahran and Sally A. McKee, Global Management of Cache Hierarchies , The ACM International Conference on Computing Frontiers (CF'10), Italy, May 2010. (pdf)

[17] Yufu Zhang , Ankur Srivastava and Mohamed Zahran, On-Chip Sensor Driven Efficient Thermal Profile Estimation Algorithms, ACM Transactions on Design Automation of Electronic Systems,  Vol 15, issue 3, May 2010.

[18] Kim Hazelwood and Mohamed Zahran. Challenges and Opportunities at All Levels: Interactions Among Operating Systems, Compilers, and Multicore Processors, ACM SIGOPS Operating System Review. Volume 43, Issue 2. April 2009. 

[19]  Najla Alfaraj, H. Jonathan Chao, and Mohamed Zahran, NBC: Network-based Cache Coherence Protocol for Multistage NoCs, in The International SoC Design Conference (ISOCC), 2009.

[20] Bushra Ahsan and Mohamed Zahran, Managing Off-Chip Bandwidth: A Case for Bandwidth-Friendly Replacement Policy,  in The 2nd Workshop on Managed Multi-Core Systems (MMCS'09), held in  conjunction with ASPLOS 2009. (pdf)

[21]  Mohamed Zahran and Sally A. McKee, Adaptive Block Placement Policy for Cache Hierarchies,in SMART'09:3rd Workshop on Statistical and Machine learning approaches to ARchitectures and compilaTion, held  in conjunction  with  HiPEAC 2009. (pdf)

[22] Bushra Ahsan and Mohamed Zahran, Cache Performance, System Performance, and Off-Chip Bandwidth... Pick any Two , in 3rd workshop Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC), held  in conjunction  with  HiPEAC 2009. (pdf)

[23]  Yufu Zhang, Ankur Srivastava and Mohamed ZahranChip Level Thermal Profile Estimation Using On-chip Temperature   Sensors, Proc. International Conference on Computer Design (ICCD), October 2008.  (pdf)

[24]   Mohamed ZahranCache Replacement Policy Revisited, in The Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD) held in conjunction with the International Symposium on Computer Architecture (ISCA), 2007. (bib, pdf)

[25]. Mohamed Zahran, Cache Hierarchy for 100 On-Chip Cores, Fifth Annual Boston 
Area Architecture Workshop (BARC), Jan 2007. (bib, pdf)

[26] Mohamed Zahran, Kursad Albayraktaroglu, and Manoj Franklin, Non-Inclusion Property in multi-level Caches Revisited,  in the International Journal of  Computers and Their Applications Special Issue on Techniques and Architectures for High Performance and Energy Efficient Computing Systems, Vol 14, Num 2, June 2007. ( bib, pdf)
[27] Mohamed Zahran and Manoj Franklin, RHT: A Context-Based Return Address Predictor, in The 2006 International Conference on Computer Design (CDES06), LasVegas, 2006. (bibpdf)

[28] Mohamed Zahran and Anasua Bhowmik, Bandwidth-Friendly Cache Hierarchy, in The 2006 International Conference on Computer Design (CDES06), Las Vegas,  2006. (bibpdf)

[29] Mohamed Zahran  and Anasua Bhowmik, Hybrid Compiler and Microarchitecture Technique for Cache Traffic Optimization, in 9th Workshop on Interaction between Compilers and Computer Architectures (INTERACT 9), held in Conjunction with the 11th International Symposium on High-Performance Computer Architecture (HPCA-11), 2005. (bibpdf)

[30]  Francois Cantonnet, Yiyi Yao,  Mohamed Zahran and Tarek El-Ghazawi,  Productivity Analysis of the UPC Language, in 3rd International Workshop on Performance Modeling, Evaluation, and Optimization of Parallel and Distributed Systems  (PMEO-PDS), to be held in conjunction with the International Parallel and Distributed Processing Symposium (IPDPS 2004).

[31] Mohamed Zahran and Manoj Franklin, Dynamic Thread Resizing for Speculative Multithreaded Processors, in International Conference on Computer Design (ICCD), San Jose, CA, October, 2003. (ps)(pdf) (Best Paper Award)

[32] Mohamed Zahran, Manoj Franklin and Renju Thomas, Confidence Estimation  for Register Value  Communication in Speculative Multithreaded Architectures,  in first value prediction workshop (VPW1),      held in conjunction with the 30th Annual International  Symposium on Computer Architecture (ISCA), San Diego, California, 2003. (ps)(pdf)

[33] Mohamed ZahranOn Cache Memory Hierarchy for Chip-Multiprocessor,  in MEDEA workshop held in conjunction with PACT 2002 Conference,  Charlottesville, Virginia, 2002. Also Appeared in ACM Computer Architecture News, Vol 31, No. 1, March 2003.

[34] Mohamed Zahran and Manoj Franklin,  Return Address Prediction in Speculative  Multithreaded Environments, in  Int'l Conference on Hi-Performance Computing,  Bangalore, India, 2002. (ps)(pdf)

[35] Mohamed  Zahran and Manoj Franklin, A Feasibility Study of Hierarchical Multithreading, in International Parallel and  Distributed Processing Symposium (IPDPS 2002), Marriott Marina, Fort Lauderdale, Florida, 2002. (ps) (pdf)

[36] Mohamed  Zahran and Manoj Franklin, Hierarchical Multi-threading For Exploiting Parallelism at Multiple Granularities, Workshop on MULTITHREADED EXECUTION, ARCHITECTURE and COMPILATION (MTEAC-5),  Austin,  Texas, 2001. (ps) (pdf)

[37]  Mohamed Zahran, Ashraf Abdel-Wahab and Samir Shaheen, Adaptive Genetic Algorithm for Multiprocessor Scheduling,  poster presentation at the Genetic and Evolutionary Computation Conference (GECCO), Orlando, 1999.

Selected Presentations & Talks (for complete list please check my CV ):

          [1] Toward Exascale Machine: Challenges and Opportunities, IBM T. J.Watson lab , April  2017.

          [2] Architecture Support for Big Data, Bloomberg,  November 2016.

          [3] Panel at IBM Research Workshop on Architectures for Cognitive Computing and Datacenters, IBM T. J. Watson lab , October 2016.

          [4]  Heterogeneous Computing: Hardware and Software Perspective, ACM Applicative, June 2016.

          [5] "Off-Chip Bandwidth: The New Wall in The Multicore Era", in CS Departmental seminar series, University of Delaware, March 2009.

          [6 ] "Attacking The Von-Neumann Bottleneck: Smart and Scalable Cache Hierarchy in The Chip Multiprocessor Era",
                IBM T. J. Watson, Feb 2007.